With the advent of EDA, design of complex hardware systems no longer begins with a hardware circuit diagram. Instead, circuit design typically begins with a software program that describes the behaviour or functionality of the hardware system. In one exemplary approach, the behaviour or functionality of an electronic circuit design may be described using hardware description language (HDL) (e.g., VHDL and Verilog). Circuit designers may use logical and physical synthesis tools to generate a net list which includes a list of components or instances included in the circuit and interconnections between the various components. At the synthesis level, designers may generate alternative architectures for an electronic circuit being designed by modifying constraints (such as clock, number and type of data path elements, and desired number of clock cycles). The net list and information about the layout of the circuit may be used to determine the optimal placement of the various components of the circuit and their routing. The physical circuit embodying the design may then be created in the design process.
As part of the electronic design automation process, the timing characteristics of the circuit design are evaluated. This may be done before detailed placement and routing of the circuit instances during the logical synthesis portion of the circuit design. Timing analysis may alternatively be performed following placement and routing during physical placement of instances during the electronic design automation process. Although the dynamic timing characteristics may be evaluated, often the static timing characteristics of the circuit is determined during this timing analysis. For example, for a given circuit clock speed, a circuit path require time may be determined. The require time is the time allowed for a signal to propagate through a particular circuit path and which meets the circuit timing requirements. The path delay time of the designed version of the electronic circuit is determined and compared with the require time to evaluate whether the signal delay time along the path (path delay) meets the require time for that path. It is common for a path slack to be determined for the various circuit paths in the circuit with the path slack being the difference between the require time and path delay. In this approach, a zero or positive path slack indicates the path complies with timing requirements. In contrast, a negative path slack indicates that the circuit path fails to meet the timing requirements at the clock speed at which it is desired to operate the circuit. By altering the positioning of circuit components or instances relative to one another, in many cases it is possible to alter the path delay and thereby the slack for a given circuit path. Desirably, the path delay is adjusted until all of the circuit paths meet or exceed the require time.
To assist in the timing evaluation process, pin slacks for the various pins of the circuit components included in the various circuit paths may be determined. In one common approach, pin slack is defined as the worst path slack of all circuit paths connected to the particular pin or which passes through the particular pin.
In a known approach for replacing circuit components or instances to improve timing characteristics of an electronic circuit design in an EDA process, the individual circuit path having the worst slack is selected. The placement of instances along this selected individual circuit path relative to one another is adjusted, typically to reduce the length of circuit interconnects between the instances. The goal of this approach is to improve the timing characteristics (slack) for this particular circuit path. The next worst case path may then be selected, circuit instances along the path may be relocated relative to one another, and timing again rechecked. In an ideal situation, this individual path by path iterative process eventually results in an electronic circuit design that meets the require time for all circuit paths at a designated circuit speed. Alternatively, the clock speed may be slowed to increase the require time as a way of reaching closure of the circuit design, that is a design in which all of the circuit paths meet the require time. The adjustment of the positioning of circuit instances along an individual path relative to one another can result in a degradation of the timing characteristics of other circuit paths, such as other paths connected to the selected path. As a result, placement of instances to achieve the required timing for the various circuit paths can be more time consuming and difficult to achieve.
Therefore, a need exists for improvements in electronic design automation to facilitate the achievement of an electronic circuit design which meets required timing characteristics for the circuit.